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Not for New Designs
CPC7583
Line Card Access Switch
Features
* Small 20-pin or 28-pin SOIC or 28-pin DFN * DFN version provides 65% PCB area reduction over 4th generation EMRs * Monolithic IC reliability * Low, matched, RON * Eliminates the need for zero-cross switching * Flexible switch timing for transition from ringing mode to talk mode. * Clean, bounce-free switching * SLIC tertiary protection via integrated current limiting, voltage clamping and thermal shutdown * 5 V operation with power consumption < 10.5 mW * Intelligent battery monitor * Logic-level inputs, no external drive circuitry required * SOIC versions pin-compatible with Legerity 7583/8583 family
Description
The CPC7583 is a monolithic 10-pole line card access switch in a 20- or 28-pin SOIC or a 28-pin DFN package. It provides the necessary functions to replace three 2-Form-C electromechanical relays on analog line cards and combined voice and data line cards found in central office, access, and PBX equipment. The device contains solid state switches for tip and ring line break, ringing injection/ringing return, and test access. The CPC7583 requires only a +5 V supply and offers break-before-make or make-before-break switch operation.
Ordering Information
CPC7583 part numbers are specified as shown here: B - 28-pin SOIC delivered 29/Tube, 1000/Reel M - 28-pin DFN delivered 33/Tube, 1000/Reel Z - 20-pin SOIC delivered 40/Tube, 1000/Reel
Applications
* * * * * * * * Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks
TTESTIN (TCHANTEST) TTESTOUT (TDROPTEST) 10 8 TRING SW7 Tip
Secondary Protection
CPC7583 x x xx
TR - Add for Tape & Reel Version A - With Protection SCR B - Without Protection SCR C - With Extra Logic State and With Protection SCR D - With Extra Logic State and Without Protection SCR
+5 Vdc 5 12 VDD
TLINE
7
X X SW5 X SW3 X
CPC7583 X SW9
6 TBAT
SW1 SLIC SW2
Ring
RLINE 22
X
X SW6 X SW4
X SW10 X
SCR and Trip Circuit 1
VREF
Switch Control Logic
SW8 RTESTOUT (RDROPTEST) 19 20
300 (min.)
L A T C H
23 RBAT 17 16 15 18
INTESTIN INRINGING INTESTOUT LATCH
24
FGND
28 VBAT
14 13 DGND
TSD
VBAT RTESTIN (RCHANTEST)
RINGING
NOTE: Pin assignments are for the 28 pin package.
Pb
DS-CPC7583-R06
RoHS
2002/95/EC
e3
1
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CPC7583
1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.6.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6.4 TESTOUT Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.6.5 Ringing Test Return Switch, SW7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6.6 Ringing Test Switch, SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6.7 TESTIn Switches, SW9 and SW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.8 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.9 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.9.1 Truth Table for CPC7583xA and CPC7583xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.9.2 Truth Table for CPC7583xC and CPC7583xD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 TSD Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mechanical Dimensions and PCB Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 CPC7583Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 CPC7583B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 CPC7583M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 CPC7583Z (20-Pin SOIC) - Tape and Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 CPC7583B (28-Pin SOIC) - Tape and Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 CPC7583M (28-Pin DFN) - Tape and Reel Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15 15 15 15 16 16 16 16 16 16 17 17 17 18 18 18 18 19 20 20 20 20 21 21 21 21
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R06
CPC7583
1. Specifications
1.1 Package Pinout 1.2 Pinout Description 20 28 Pin Pin
28 VBAT 27 NC 26 NC 25 NC 24 RTESTin 23 RBAT 22 RLINE 21 NC 20 RRINGING 19 RTESTout 18 LATCH 17 IN TESTin 16 INRINGING 15 INTESTout
CPC7583B & CPC7583M
FGND 1 NC 2 NC 3 NC 4 TTESTin 5 TBAT 6 TLINE 7 TRINGING 8 NC 9 TTESTout 10 NC 11 VDD 12 TSD 13 DGND 14
Name FGND NC NC NC TTESTin TBAT TLINE NC NC VDD TSD DGND Fault ground.
Description
1
1 2 3 4
No connection. No connection. No connection. Tip lead of the TESTin bus. Tip lead of the SLIC. Tip lead of the line side. Not connected. No connection. +5 V supply. Temperature shutdown pin. Digital ground.
2 3 4 5 6 7 8 9
5 6 7 8 9 10 11 12 13
TRINGING Ringing generator return. TTESTout Tip lead of the TESTout bus.
10 14
11 15 INTESTout Logic control input. 12 16 INRINGING Logic control input. 13 17 14 18 15 19 21 INTESTin Logic control input. LATCH Data latch enable control input. RTESTout Ring lead of the TESTout bus. NC RLINE RBAT RTESTin NC NC NC VBAT No connection. Ring lead of the line side. Ring lead of the SLIC. Ring lead of the TESTin bus. No connection. No connection. No connection. Battery supply.
16 20 RRINGING Ringing generator source.
CPC7583Z
FGND 1 TTESTIN 2 TBAT 3 TLINE 4 20 VBAT 19 RTESTIN 18 RBAT 17 RLINE 16 RRINGING 15 RTESTOUT 14 LATCH 13 INTESTIN 12 INRINGING 11 INTESTOUT
17 22 18 23 19 24 25 26 27 20 28
TRINGING 5
TTESTOUT 6 NC 7 VDD 8 TSD 9 DGND 10
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CPC7583
1.3 Absolute Maximum Ratings Parameter Operating temperature Storage temperature Operating relative humidity +5 V power supply (VDD) Battery Supply DGND to FGND separation Logic input voltage Logic input to switch output isolation Switch open contact isolation (SW1, SW2, SW3, SW5, SW6, SW7, SW9, SW10) Switch open contact isolation (SW4) Switch open contact isolation (SW8) Minimum Maximum -40 -40 5 -0.3 -5 -0.3 +110 +150 95 7 -85 +5 VDD +0.3 320 Unit C C % V V V V V 1.5 General Conditions Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device at 25C and are the result of engineering evaluations. They are provided for informational purposes only and are not part of the manufacturing testing requirements. Specifications cover the operating temperature range TA = -40C to +85C. Also, unless otherwise specified all testing is performed with VDD = +5Vdc, logic low input voltage is 0Vdc and logic high input voltage is +5Vdc. ESD Rating (Human Body Model) 1000 V 1.4 ESD Rating
-
320
V
-
465 235
V V
Absolute maximum electrical ratings are at 25C
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied.
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R06
CPC7583
1.6 Switch Specifications 1.6.1 Break Switches, SW1 and SW2 Parameter Off-state leakage current +25 C +85 C -40 C RON +25 C +85 C -40 C RON match DC current limit +25 C +85 C -40 C Dynamic current limit (t 0.5 s) Break switches on, ringing switches off, apply 1 kV 10x1000 s pulse, with appropriate protection in place. VSW (TLINE, RLINE) = 320 V, logic inputs = gnd VSW (TLINE, RLINE) = 330 V, logic inputs = gnd VSW (TLINE, RLINE) = 310 V, logic inputs = gnd ISW VSW (on) = 10 V ISW 80 225 150 400 2.5 425 A mA ISW(on) = 10 mA, 40 mA, RBAT and TBAT = -2 V Per on-resistance test condition of SW1 & SW2 14.5 RON RON 20.5 10.5 0.15 28 0.8 VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 A Test Conditions Symbol Minimum Typical Maximum Unit
Logic input to switch output isolation +25 C +85 C -40 C dv/dt sensitivity 0.1 0.3 0.1 200 V/s 1 A
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5
CPC7583
1.6.2 Ringing Return Switch, SW3 Parameter Off-state leakage current +25 C +85 C -40 C RON +25 C +85 C -40 C DC current limit +25 C +85 C -40 C Dynamic current limit (t 0.5 s) Break switches off, ringing switches on, apply 1 kV 10x1000 s pulse, with appropriate protection in place. VSW (TRING, TLINE) = 320 V, logic inputs = gnd VSW (TRING, TLINE) = 330 V, logic inputs = gnd VSW (TRING, TLINE) = 310 V, logic inputs = gnd ISW VSW (on) = 10 V ISW 70 120 85 210 2.5 A mA ISW(on) = 0 mA, 10 mA RON 60 85 45 110 VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 A Test Conditions Symbol Minimum Typical Maximum Unit
Logic input to switch output isolation +25 C +85 C -40 C dv/dt sensitivity 0.1 0.3 0.1 200 V/s 1 A
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R06
CPC7583
1.6.3 Ringing Switch, SW4 Parameter Off-state leakage current +25 C +85 C -40 C On Voltage VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V ISW (on) = 1 mA IRINGING ISW IRINGING RON ISW 0.05 0.1 0.05 1.5 0.1 450 10 1 1 1 3 0.25 150 2 15 V mA mA A A A Test Conditions Symbol Minimum Typical Maximum Unit
Ringing generator current to ground during Inputs set for ringing mode ringing On steady-state current* Inputs set for ringing mode Surge current* Release current RON Logic input to switch output isolation +25 C +85 C -40 C dv/dt sensitivity VSW (RRING, RLINE) = 320 V, logic inputs = gnd VSW (RRING, RLINE) = 330 V, logic inputs = gnd VSW (RRING, RLINE) = 310 V, logic inputs = gnd ISW (on) = 70 mA, 80 mA
0.1 ISW 0.3 0.1 200 V/s 1 A
-
*Secondary protection and ringing source current limiting must prevent exceeding this parameter.
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CPC7583
1.6.4 TESTOUT Switches, SW5 and SW6 Parameter Off-state leakage current +25 C +85 C -40 C RON +25 C +85 C -40 C DC current limit +25 C +85 C -40 C Dynamic current limit (t 0.5 s) Break switches in on state, ringing switches off, apply 1 kV at 10x1000 s pulse, with appropriate secondary protection in place. VSW (TTESTout, TLINE, RTESTout, RLINE) = 320 V, logic inputs = gnd VSW (TTESTout, TLINE, RTESTout, RLINE) = 330 V, logic inputs = gnd VSW (TTESTout, TLINE, RTESTout, RLINE) = 310 V, logic inputs = gnd ISW 2.5 A VSW (on) = 10 V 80 140 100 210 250 mA ISW(on) = 10 mA, 40 mA RON 35 50 26 70 VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V VSW (differential) = -330 V to gnd VSW (differential) = +260 V to -60 V VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 A Test Conditions Symbol Minimum Typical Maximum Unit
Logic input to switch output isolation +25 C +85 C -40 C dv/dt sensitivity ISW ISW ISW 0.1 0.3 0.1 200 1 1 1 A A A V/s
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R06
CPC7583
1.6.5 Ringing Test Return Switch, SW7 Parameter Off-state leakage current +25 C +85 C -40 C RON +25 C +85 C -40 C DC current limit +25 C +85 C -40 C Logic input to switch output isolation +25 C +85 C -40 C dv/dt sensitivity VSW (TRING, TTESTin) = 320 V, logic inputs = gnd VSW (TRING, TTESTin) = 330 V, logic inputs = gnd VSW (TRING, TTESTin) = 310 V, logic inputs = gnd ISW 0.1 0.3 0.1 200 V/s 1 A VSW (on) = 10 V ISW 70 120 80 210 mA ISW(on) = 10 mA, 40 mA RON 60 85 45 100 VSW (differential) = -320 V to gnd VSW (differential) = +260 to -60 V VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 A Test Conditions Symbol Minimum Typical Maximum Unit
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CPC7583
1.6.6 Ringing Test Switch, SW8 Parameter Off-state leakage current +25 C +85 C -40 C On Voltage RON Release Current Logic input to switch output isolation +25 C +85 C -40 C dv/dt sensitivity VSW (RRING, RTESTin) = 320 V, logic inputs = gnd VSW (RRING, RTESTin) = 330 V, logic inputs = gnd VSW (RRING, RTESTin) = 310 V, logic inputs = gnd ISW 0.1 0.3 0.1 200 V/s 1 A ISW(ON) = 1 mA ISW(ON) = 70 mA, 80 mA RON VSW (differential) = -60 V to +175 V ISW 0.05 0.1 0.05 0.75 35 450 1.5 V A 1 A Test Conditions Symbol Minimum Typical Maximum Unit
1.6.7 TESTIn Switches, SW9 and SW10 Parameter Off-state leakage current +25 C +85 C -40 C RON +25 C +85 C -40 C DC current limit +25 C +85 C -40 C Logic input to switch output isolation +25 C +85 C -40 C dv/dt sensitivity VSW (TTESTin, RTESTin) = 320 V, logic inputs = gnd VSW (TTESTin, RTESTin) = 330 V, logic inputs = gnd VSW (TTESTin, RTESTin) = 310 V, logic inputs = gnd ISW 0.1 0.3 0.1 200 V/s 1 A VSW (on) = 10 V ISW 80 160 110 210 250 mA ISW(on) = 10 mA, 40 mA RON 35 50 26 70 VSW (differential) = -320 V to gnd VSW (differential) = -60 V to +260 V VSW (differential) = -330 V to gnd VSW (differential) = -60 V to +270 V VSW (differential) = -310 V to gnd VSW (differential) = -60 V to +250 V ISW 0.1 0.3 0.1 1 A Test Conditions Symbol Minimum Typical Maximum Unit
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CPC7583
1.7 Additional Electrical Characteristics Parameter Digital Inputs Input low voltage Input high voltage Input leakage current (high) Input leakage current (low) Voltage Requirements VDD VBAT1
1
Test Conditions VDD = 5.5 V, VBAT = -75 V, VIH = 5 V VDD = 5.5 V, VBAT = -75 V, VIL = 0 V
Symbol VIL VIH IIH IIL
Minimum 3.5 -
Typical 0.1 0.1
Maximum 1.5 1
Unit
V
A 1
-
VDD VBAT
4.5 -19
5.0 -
5.5 -72
V V
VBAT is used only for internal protection circuitry. If VBAT goes more positive than -10 V, the device will enter the all-off state and will remain in the all-off state until the battery goes more negative than -15 V
Power Requirements Power consumption in talk and all-off states Power consumption in any other state VDD current in talk and all-off states VDD current in any other state VDD = 5 V, VBAT = -48 V, measure IDD and IBAT VDD = 5 V, VBAT = -48 V, measure IDD and IBAT P P IDD VDD = 5 V, VBAT = -48 V IDD 1.0 4 1.9 10 A 3.5 5.0 0.7 7.5 mW 10.5 1.5 mA
IBAT VBAT current in any state VDD = 5V, VBAT = -48 V Temperature Shutdown Requirements (temperature shutdown flag is active low) Shutdown activation temperature Shutdown circuit hysteresis Not production tested - limits are guaranteed by design and Quality Control sampling audits. TSD_on TSD_off 110 10
125 -
150 25
C C
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CPC7583
1.8 Protection Circuitry Electrical Specifications Parameter Voltage drop at continuous current (50/60 Hz) Voltage drop at surge current Surge current Trigger current Hold current Gate trigger voltage +25 C +85 C +25 C +85 C IGATE = ITRIGGER Conditions Symbol Minimum Typical Maximum Unit
Parameters Related to the Diodes in the Diode Bridge Apply dc current limit of break switches Apply dynamic current limit of break switches Forward Voltage Forward Voltage ITRIG ITRIG IHOLD IHOLD VTBAT or VRBAT IVBAT VTBAT or VRBAT 100 VBAT -4 2.8 5 3.5 V -
Parameters Related to the Protection SCR (CPC7583xA and CPC7583xC) 200 120 265 170 -3 -5 * VBAT -2 1.0 V A V V mA A
Reverse leakage current VBAT = -48 V On-state voltage 0.5 A, t = 0.5 s 2.0 A, t = 0.5 s
*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate.
1.9 Truth Tables 1.9.1 Truth Table for CPC7583xA and CPC7583xB State Talk TESTout TESTin Simultaneous TESTin and TESTout Ringing Ringing Generator Test Latched All Off
1 2
INRINGING 0 0 0 0 1 1 X 1 1 X
INTESTIN 0 0 1 1 0 1 X 0 1 X
INTESTOUT 0 1 0 1 0 0 X 1 1 X
Latch
TSD
TESTIN Switches Off Off On
Break Switches On Off Off Off Off Off
Ringing Test Switches Off Off Off Off Off On
Ringing Switches Off Off Off Off On Off
TESTOUT Switches Off On Off On Off Off
0 1 or Floating 1
On Off Off
1 0 0 X 02
Unchanged Unchanged Unchanged Unchanged Unchanged Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off
If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally. Forcing TSD to ground overrides the logic input pins and forces an all off state.
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1.9.2 Truth Table for CPC7583xC and CPC7583xD State Talk TESTout TESTin Simultaneous TESTin and TESTout Ringing Ringing Generator Test Simultaneous TESTout and Ringing Generator Test Latched All Off
1
INRINGING 0 0 0 0 1 1
INTESTIN 0 0 1 1 0 1
INTESTOUT 0 1 0 1 0 0
Latch
TSD
TESTIN Switches Off Off On On Off
Break Switches On Off Off Off Off Off
Ringing Test Switches Off Off Off Off Off On
Ringing Switches Off Off Off Off On Off
TESTOUT Switches Off On Off On Off Off
0
1 or Floating 1
Off
1
1
1
Off
Off
On
Off
On
X 1 X
X 0 X
X 1 X
1 0 X 02
Unchanged Unchanged Unchanged Unchanged Unchanged Off Off Off Off Off Off Off Off Off Off
If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally. 2Forcing T to ground overrides the logic input pins and forces an all off state. SD
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CPC7583
2. Functional Description
2.1 Introduction The CPC7583 has the following states: * Talk. Loop break switches SW1, and SW2 closed, all other switches open. * Ringing. Ringing switches SW3, SW4 closed, all other switches open. * TESTout. Testout switches SW5, SW6 closed, all other switches open. * Ringing generator test. SW7, SW8 closed, all other switches open. * TESTin. Testin switches SW9 and SW10 closed. * Simultaneous TESTin and TESTout. SW9, SW10, SW5, and SW6 closed, all other switches open. * Simultaneous test out and ringing generator test. SW5, SW6, SW7, and SW8 closed, all other switches open (only on the xC and xD versions). * All Off. All switches open. See "Truth Tables" on page 12 for more information. The CPC7583 offers break-before-make and make-before-break switching from the ringing state to the talk state with simple logic level input control. Solid-state switch construction means no impulse noise is generated when switching during ringing cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State-control is via logic-level input so no additional driver circuitry is required. The linear line break switches SW1 and SW2 have exceptionally low RON and excellent matching characteristics. The ringing switch SW4 has a minimum open contact breakdown voltage of 465 V. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Integrated into the CPC7583 is an over voltage clamping circuit, active current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and hazardous potentials are diverted to ground via diodes and the integrated SCR. Power-cross potentials are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC7583 from an overvoltage fault condition, the use of a secondary protector is required. The secondary protector must limit the voltage seen at the TLINE and RLINE terminals to a level below the maximum breakdown voltage of the switches. To
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minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7583 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. The CPC7583 operates from a +5 V supply only. This gives the device extremely low idle and active power consumption and allows use with virtually any range of battery voltage. The battery voltage is also used by the CPC7583 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7583 enters the all-off state.
2.2 Switch Logic The CPC7583 provides, when switching from the ringing state to the talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the loop break switches SW1 and SW2 using simple logic-level input. This is referred to as a make-before-break or break-before-make operation. When the line break switch contacts (SW1 and SW2) are closed (or made) before the ringing access switch contacts (SW3 and SW4) are opened (broken), this is referred to as make-before-break operation. Break-before-make operation occurs when the ringing access contacts (SW3 and SW4) are opened (broken) before the line break switch contacts (SW1 and SW2) are closed (made). With the CPC7583, the make-before-break and break-before-make operations can easily be selected by applying the proper sequence of logic inputs to INTESTout, INRINGING, and INTESTin. The logic sequences for either mode of operation are given in "Make-Before-Break Operation (Ringing to Talk Transition)" on page 15 and "Break-Before-Make Operation (Ringing to Talk Transition)" on page 15. Logic states and explanations are given in "Truth Tables" on page 12. Break-before-make operation can also be achieved using the TSD pin as an input. In "Break-Before-Make Operation (Ringing to Talk Transition)" on page 15, lines 2 and 3, it is possible to induce the switches to the all-off state by grounding TSD instead of applying input to the logic pins. This has the effect of overriding the logic inputs and forcing the device to the all-off state. For
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CPC7583
20 Hz ringing hold this input state for 25 ms. During this hold period, toggle the inputs from the ringing state to the talk state. After the 25 ms, release TSD to return switch control to the input pins INTESTout, INRINGING, INTESTin and the latch control pin. 2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) State Ringing INRINGING INTESTIN INTESTOUT 1 0 0 Latch TSD Floating Timing Break Ring Ring All Other Switches Return Access Test 1 and 2 Switch 3 Switch 4 Switches Off On On Off
Makebeforebreak
0
0
0
0
SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of ringing. In this transition Floating state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. Floating Zero-cross current has occurred
On
Off
On
Off
Talk
0
0
0
On
Off
Off
Off
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) State Ringing All off All off Talk INRINGING INTESTIN INTESTOUT 1 1 1 0 0 0 0 0 0 1 0 1 0 Latch TSD Floating Timing Break Ring Ring All Other Switches Return Access Test 1 and 2 Switch 3 Switch 4 Switches Off Off Off On On Off Off Off On On Off Off Off Off Off Off
Hold this state for one-half of Floating ringing cycle. SW4 waiting for zero current to turn off. Floating Floating Zero current has occurred. SW4 has opened Close break switches
2.3 Alternate Break-Before-Make Operation Note that break-before-make operation can also be achieved using TSD as an input. In lines 2 and 3 of the table "Break-Before-Make Operation (Ringing to Talk Transition)" on page 15, instead of using the logic input pins to force the all-off state, force TSD to ground. This overrides the logic inputs and also forces the all off state. Hold this state for one-half of the ringing cycle. During this TSD forced all-off state, change the inputs from the power ringing state (INRING = 1, INTESTIN = 0, INTESTOUT = 0) to the talk state (INRING = 0, INTESTIN = 0, INTESTOUT = 0). After the hold period, release TSD to return switch control to the input pins which will set the talk state.
2.4 Data Latch The CPC7583 has an integrated data latch. The latch operation is controlled by logic-level input at the LATCH pin. The data input of the latch are the input pins, while the output of the data latch is an internal node used for state control. When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected by a change in switch state. When the LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from
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CPC7583
logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control. 2.8 Battery Voltage Monitor The CPC7583 also uses the VBAT voltage to monitor battery voltage. If battery voltage is lost, the CPC7583 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the system battery voltage goes more positive than -10 V, and remains in the all-off state until the battery voltage goes more negative than -15 V. This battery monitor feature draws a small current from the battery (less than 1 A typical) and will add slightly to the device's overall power dissipation.
2.5 TSD Behavior Setting TSD to +5V allows switch control using the logic inputs. This setting, however, also disables the thermal shutdown circuit and is therefore not recommended. When using logic control via the input pins, TSD should be allowed to float. As a result, the two recommended states when using TSD as a control are 0, which forces the device to an all-off state, or float, which allows logic inputs to remain active. This requires the use of an open-collector type buffer.
2.9 Protection 2.9.1 Diode Bridge/SCR The CPC7583 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via FGND. Voltage is clamped to a diode drop above ground. During a negative transient of 2V to 4V more negative than the voltage source at VBAT, the SCR conducts and faults are shunted to FGND via the SCR or the diode bridge. In order for the SCR to crowbar or foldback, the on voltage (see "Protection Circuitry Electrical Specifications" on page 12) of the SCR must be less negative than the VBAT voltage. If the VBAT voltage is less negative than the SCR on voltage, or if the VBAT supply is unable to source the trigger current, the SCR will not crowbar. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to a diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the VBAT reference voltage by two to four volts, steering the fault current to ground.
2.6 Ringing Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See Clare application note AN-144, Impulse Noise Benefits of Line Card Access Switches for more information. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 in series with the ringing generator is recommended.
2.7 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7583. Switch state control is powered exclusively by the +5 V supply. As a result, the CPC7583 exhibits extremely low power consumption during both active and idle states. The battery voltage is not used for switch control but rather as a supply for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when the voltage at TBAT or RBAT drops 2 to 4 V below the applied voltage on the VBAT pin. This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes.
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2.9.2 Current Limiting function If a lightning strike transient occurs when the device is in the talk state, the current is passed along the line to the integrated protection circuitry and restricted by the dynamic current limit response of the active switches. During the talk state when a 1000V 10x1000 S pulse (GR-1089-CORE lightning) is applied to the line though a properly clamped external protector, the current into TLINE or RLINE will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 s. If a power-cross fault occurs with the device in the talk state, the current is passed though break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current at TLINE or RLINE will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state. 2.11 External Protection Elements The CPC7583 requires only over-voltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for additional protection on the SLIC side. The secondary protector must limit voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7583. A foldback or crowbar type protector is recommended to minimize stresses on the CPC7583. Consult Clare's application note, AN-100, "Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces" for equations related to the specifications of external secondary protectors, fused resistors and PTCs.
2.10 Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110 C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, the voltage out of the TSD pin will read 0 V. Normal output of TSD is VDD. If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to the all-off state. At this point the current measured into TLINE or RLINE will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the deactivation level of the thermal shutdown circuit. This will permit the device to return to normal operation. If the transient has not passed, current will flow up to the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground.
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CPC7583
3. Manufacturing Information
3.1 Mechanical Dimensions and PCB Land Patterns 3.1.1 CPC7583Z
20-Lead SOIC Package
12.60 / 13.00 (0.496 / 0.512) 0.23 / 0.32 (0.009 / 0.013)
Recommended PCB Land Pattern
0.40 / 1.27 (0.016 / 0.050) 7.40 / 7.60 (0.291 / 0.299) 10.00 / 10.65 (0.394 / 0.419) 9.30 (0.366) 2.05 (0.081)
Pin 1
0.25 / 0.75 x 45 (0.010 / 0.029 x 45) 0.508 / 0.762 (0.020 / 0.030) 2.35 / 2.65 (0.093 / 0.104) 0 - 8 1.27 (0.05) 0.60 (0.024)
1.27 TYP (0.050 TYP)
0.33 / 0.51 (0.013/ 0.020)
0.10 / 0.30 (0.004 / 0.012)
Dimensions mm MIN / mm MAX (inches MIN / inches MAX)
3.1.2 CPC7583B
28-Lead SOIC Package
0.2311 / 0.3175 (0.0091 / 0.0125) 17.983 / 18.085 (0.708 / 0.712)
Recommended PCB Land Pattern
7.391 / 7.595 (0.291 / 0.299)
10.109 / 10.516 (0.398 / 0.414)
0.508 / 1.016 (0.020 / 0.040) 9.50 (0.374)
1.80 (0.071)
Pin 1
0.254 / 0.737 x 45 (0.010 / 0.029 x 45) 2.438 / 2.642 (0.096 / 0.104) 2.235 / 2.438 (0.088 / 0.096) 1.27 (0.05) 0.60 (0.024)
1.27 TYP (0.050 TYP)
0.366 / 0.467 (0.014/ 0.018)
0.660 0.102 (0.026 0.004)
Dimensions mm MIN / mm MAX (inches MIN / inches MAX)
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3.1.3 CPC7583M
28-Lead DFN Package
11.0 (0.433) 0.33 +0.07,-0.05 (0.013 +0.003, -0.002) 0.75 (0.030)
Recommended PCB Land Pattern
Pin 1
7.0 (0.276)
5.00.05 (0.1970.002)
6.70 (0.264)
1.05 (0.045)
0.550.10 (0.0220.004) 0.900.10 (0.036 0.004) 0.20 (0.008) Seating Plane 0.02 +0.03, -0.02 (0.001 +0.0012, -0.001)
7.50.05 (0.2960.002)
Bottom side metallic pad
Pin 1
0.75 (0.03)
0.35 (0.016)
Dimensions mm (inches)
NOTE: Because the metallic pad on the bottom of the DFN package is connected to the substrate of the die, Clare recommends that no printed circuit board traces cross this area to avoid potential shorting issues.
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CPC7583
3.2 Tape and Reel Specifications 3.2.1 CPC7583Z (20-Pin SOIC) - Tape and Reel Dimensions
P=12.00 (0.47) 330.2 DIA. (13.00 DIA) Top Cover Tape Thickness 0.102 MAX (0.004 MAX) B0=13.40 +0.15 (0.53+0.01)
W=24.00+0.3 (0.94+0.01)
Embossed Carrier
K0=3.20 +0.15 (0.13+0.01) Embossment K1=2.60 +0.15 (0.10+0.01)
A0=10.75 +0.15 (0.42+0.01)
Dimensions mm (inches)
3.2.2 CPC7583B (28-Pin SOIC) - Tape and Reel Dimensions
330.2 DIA. (13.00 DIA) Top Cover Tape Thickness 0.102 MAX (0.004 MAX) K1=2.60 (0.10) K0=3.20 (0.13)
A0=10.75 (0.42)
B0=18.50 (0.73)
W=24.000.3 (0.940.01)
Embossed Carrier
Embossment
P=12.00 (0.47)
Dimensions mm (inches)
3.2.3 CPC7583M (28-Pin DFN) - Tape and Reel Dimensions
330.2 DIA. (13.00 DIA) Top Cover Tape Thickness 0.102 MAX (0.004 MAX) B0=11.35 (0.45)
W=24.00+0.3 (0.94+0.01)
Embossed Carrier K0=1.35 (0.05) Embossment P=12.00 (0.47) A0=7.35 (0.29)
Dimensions mm (inches)
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CPC7583
3.3 Soldering 3.3.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity for this product using IPC/JEDEC standard J-STD-020. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-033 per the labeled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 3 for the DFN package. 3.3.2 Reflow Profile For proper assembly, this component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy.
3.4 Washing Clare does not recommend ultrasonic cleaning of this part.
Pb
RoHS
2002/95/EC
e3
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Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS-CPC7583 - R06 (c) Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 10/15/2009
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